1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for testing a semiconductor device, and more particularly to a semiconductor memory device requiring performance of a plurality of tests for each of plurality of memory circuits and a method for testing the same.
2. Description of the Background Art
FIG. 4 is a block diagram showing a structure of a synchronous dynamic random access memory (hereinafter referred to as SDRAM) 30 connected to a tester 20. First, SDRAM 30 will be described.
With reference to FIG. 4, SDRAM 30 includes a control signal generation circuit 31, a command decoder 32, an address buffer 33, a clock buffer 34, memory arrays 35a-35d, row decoders (RD) 36a-36d, column decoders (CD) 37a-37d, sense amplifiers+input/output control circuits 38a-38d and a data input/output circuit 39.
Control signal generation circuit 31 receives a variety of control signals such as /RAS, /CAS and /WE supplied from an external source and generates and supplies a variety of internal control signals to command decoder 32. Command decoder 32 decodes these internal control signals, generates a variety of command signals CMD0-CMDi (where i is an integer equal to or larger than 0) and controls SDRAM 30 as a whole by these command signals CMD0-CMDi.
Address buffer 33 takes in address signals A0-Aj (where j is an integer equal to or larger than 0) supplied from an external source as row address signals X0-Xj or column address signals Y0-Yj, and supplies row address signals X0-Xj and column address signals Y0-Yj to row decoders 36a-36d and column decoder 37a-37d, respectively. Clock buffer 34 receives a clock signal CLK supplied from an external source, generates and supplies to SDRAM 30 as a whole an internal clock signal CLKxe2x80x2. SDRAM 30 operates in synchronization with internal clock signal CLKxe2x80x2.
Memory arrays 35a-35d constitute banks #0-#3, respectively. Each of memory arrays 35a-35d is arranged as a matrix and includes a plurality of memory cells each storing one-bit data. Each memory cell is located at a certain address designated by a row address and a column address.
Row decoders 36a-36d designate row addresses of memory arrays 35a-35d, respectively in response to row address signals X0-Xj supplied from address buffer 33. Column decoders 37a-37d designate column addresses of memory arrays 35a-35d, respectively in response to column address signals Y0-Yj supplied from address buffer 33.
Sense amplifiers+input/output control circuits 38a-38d connect memory cells at addresses designated by row decoders 36a-36d and column decoder 37a-37d, respectively, to one ends of data input/output line pairs IOPs. Another ends of data input/output line pairs IOPs are connected to data input/output circuit 39. Data input/output circuit 39 supplies data input from an external source to a selected memory cell via data input/output line pair IOP in a writing mode, and supplies as an output data read from a selected memory cell to an external device in a reading mode.
FIG. 5 is a partially omitted circuit block diagram showing a structure of memory array 35a and sense amplifier+input/output control circuit 38a of SDRAM 30 shown in FIG. 4.
With reference to FIG. 5, memory array 35a includes a plurality of memory cells MCs arranged in a matrix, word lines WLs arranged for respective rows, and bit line pairs BLs, /BLs arranged for respective columns.
Each memory cell MC is of a well known type in the art and includes an access N channel MOS transistor and an information storing capacitor. Word line WL transmits an output of row decoder 36a and activates a memory cell MC in a selected row. Bit line pair BL, /BL serves for input/output of a data signal to/from a selected memory cell MC.
Sense amplifier+input/output control circuit 38a includes column select gates 41s, sense amplifiers 42s and equalizers 43s arranged corresponding to respective columns. Column select gate 41 includes a pair of N channel MOS transistors connected between bit line pair BL, /BL and data input/output line pair IO, /IO. A gate of each N channel MOS transistor is connected to column decoder 37a via a column select line CSL. When column select line CSL is activated by column decoder 37a to an xe2x80x9cHxe2x80x9d (logical high) level which is a select level, a pair of N channel MOS transistors is rendered conductive coupling bit line pair BL, /BL and data input/output line pair IO, /IO.
Sense amplifier 42 amplifies a minor potential difference between bit line BL and bit line /BL to the level of power supply voltage Vcc in response to activation of sense amplifier activation signals SE, /SE respectively to an xe2x80x9cHxe2x80x9d level and to an xe2x80x9cLxe2x80x9d (logical low) level. Equalizer 43 equalizes the potentials of bit line BL and bit line /BL to a bit line voltage VBL (=Vcc/2) in response to activation of a bit line equalization signal BLEQ to an xe2x80x9cHxe2x80x9d level. Memory arrays 35b-35d and sense amplifiers+input/output control circuits 38b-28d are of the same structure as memory array 35a and sense amplifier+input/output control circuit 38a. Here, signals SE, /SE, BLEQ are included in command signals CMD0-CMDi shown in FIG. 4.
Next, an operation of SDRAM 30 shown in FIGS. 4 and 5 will be briefly described. In the writing mode, one of column decoders 37a-37d activates column select line CSL in a column corresponding to column address signals Y0-Yj to an activation level, that is an xe2x80x9cHxe2x80x9d level, rendering column select gate 41 conductive.
Data input/output circuit 39 supplies data to be written supplied from an external source to a bit line pair BL, /BL of a selected column via data input/output line pair IOP. Data to be written is given as a potential difference between bit line BL and bit line /BL. Then, one of row decoders 36a-36d activates word line WL of a row corresponding to row address signals X0-Xj to an xe2x80x9cHxe2x80x9d level, that is the select level, rendering an N channel MOS transistor of a memory cell MC in the row conductive. Electric charges of an amount corresponding to the potential of bit line BL or /BL is stored in the capacitor of the selected memory cell MC.
In the reading mode, first, bit line equalization signal BLEQ is pulled down to an xe2x80x9cLxe2x80x9d level and the equalization of bit lines BL and /BL is stopped. One of row decoders 36a-36d pulls up a word line WL of a row corresponding to row address signals X0-Xj to an xe2x80x9cHxe2x80x9d level that is the select level. The potentials of bit lines BL and /BL change by a minor amount according to the amount of electric charges in a capacitor of an activated memory cell MC.
Then, sense amplifier activation signals SE and /SE attain an xe2x80x9cHxe2x80x9d level and xe2x80x9cLxe2x80x9d level, respectively and sense amplifier 42 is activated. When the potential of bit line BL is higher than the potential of bit line /BL by a minor amount, the potential of hit line BL is pulled up to an xe2x80x9cHxe2x80x9d level and the potential of bit line /BL is pulled down to an xe2x80x9cLxe2x80x9d level. Conversely, when the potential of bit line /BL is higher than the potential of bit line BL by a minor amount, the potential of bit line /BL is pulled up to an xe2x80x9cHxe2x80x9d level and the potential of bit line BL is pulled down to an xe2x80x9cLxe2x80x9d level.
One of column decoders 37a-37d then activates column select line CSL of a column corresponding to column address signals Y0-Yj to an xe2x80x9cHxe2x80x9d level, that is the select level, rendering column select gate 41 of the column conductive. Data of bit line pair BL, /BL of the selected column is supplied to data input/output circuit 39 via column select gate 41 and data input/output line pair IO, /IO. Data input/output circuit 39 supplies read data to an external device.
To guarantee the quality of an SDRAM such as SDRAM 30, a variety of tests are performed before delivery. Tests include long period tests and short period tests. Long period tests include a disturb test, a long cycle type test (read modify write Y march test, for example) and so on, and short period tests include a typical function test and so on.
In the disturb test, data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is first written into all the memory cells MCs. Then, word line WL is turned to an xe2x80x9cHxe2x80x9d level that is the select level for a predetermined period (64 ms, for example) one by one (or block by block). Thus the memory cell MC data destruction caused by noise on an adjacent word line WL is accelerated. The higher the power supply voltage Vcc, the greater the effect of acceleration. Finally, data of all memory cells MCs are read and checked to determine whether the data of each memory cell MC is destroyed or not. The above described test is performed for a case in which data xe2x80x9c0xe2x80x9d is written to memory cells MCs and a case in which data xe2x80x9c1xe2x80x9d is written to memory cells MCs. The disturb test of 64 M-bit SDRAM takes 512 seconds, for example. The time period required for writing/reading of data to/from all memory cells MCs is significantly shorter than the disturb time.
In addition, in the long cycle type test, data xe2x80x9c0xe2x80x9d is first written into all the memory cells MCs. Then written data xe2x80x9c0xe2x80x9d is read and the inverted data xe2x80x9c1xe2x80x9d is written into the same address. Then written data xe2x80x9c1xe2x80x9d is read and the inverted data xe2x80x9c0xe2x80x9d is written into the same address. Here, writing/reading is performed at a longer cycle than a normal cycle. Under this condition, output level drop, word line level drop, leakage of bit lines and so on are checked. In the long cycle type test, as the writing/reading is performed at a longer cycle than the normal cycle for each memory cell MC, the test period becomes longer than that of the normal test.
Further in the typical function test, whether a basic writing operation and reading operation are correctly performed or not is checked. In this test, as only a simple writing/reading operation is performed for a memory cell MC connected to a word line WL, only a short test time, for example, of one second is required.
FIGS. 6A-6G are time charts showing operations of tester 20 and SDRAM 30 during the disturb test. Tester 20 supplies clock signal CLK, control signals /RAS, /CAS and /WE, address signals A0-Aj and so on to SDRAM 30. At the rising edge of clock signal CLK at time to, control signals /RAS, /CAS and /WE attain an xe2x80x9cLxe2x80x9d level, an xe2x80x9cHxe2x80x9d level and xe2x80x9cHxe2x80x9d level, respectively, and an active command is supplied from tester 20 to SDRAM 30. Then, address signals A0-Aj are taken in as row address signals X0-Xj and a word line WL0 corresponding to the row address signals X0-Xj is activated to an xe2x80x9cHxe2x80x9d level which is the select level.
Then at the rising edge of clock signal CLK at time t1 a predetermined time period (64 ms, for example) after the time to, control signals /RAS, /CAS and /WE attain an xe2x80x9cLxe2x80x9d level, an xe2x80x9cHxe2x80x9d level and an xe2x80x9cLxe2x80x9d level, respectively and a precharge command is supplied from tester 20 to SDRAM 30. Then, address signals A0-Aj are taken in as row address signals X0-Xj, and word line WL0 at an xe2x80x9cHxe2x80x9d level is turned to an xe2x80x9cLxe2x80x9d level and a bank having a word line WL1 to be next rendered an xe2x80x9cHxe2x80x9d level is precharged. Thus, all the word lines WLs of all banks #0-#3 each attain an xe2x80x9cHxe2x80x9d level for a predetermined time period.
FIGS. 7A and 7B schematically show a conventional test procedure. The disturb test is first performed for all banks #0-#3 and then a test (such as the typical function test) other than the disturb test are performed for all banks #0-#3. If the time required for the disturb test is Ta and the time required for another test is Tb, test time Ta+Tb is required in total.
In the conventional test procedure, however, as all signals necessary for the test of SDRAM 30 are supplied from tester 20, more than one test cannot be simultaneously performed whereby test time becomes long.
A primary object of the present invention is, therefore, to provide a semiconductor memory device and a method of testing the same allowing reduction of test time.
Thus, a semiconductor memory device according to the present invention includes a test pattern generation circuit generating a control signal and an address signal for performing a first test, a select circuit for selecting one memory circuit of a plurality of memory circuits, and a switch circuit provided corresponding to each memory circuit for supplying the control signal and the address signal generated by the test pattern generation circuit to a corresponding memory circuit when the corresponding memory circuit is selected by the select circuit, and for supplying a control signal and an address signal supplied from an external source for performing a second test to the corresponding memory circuit during other period. As the first test can be performed for the selected memory circuit while the second test is performed for other memory circuit, test time can be reduced compared with the conventional procedure where first and second tests cannot be simultaneously performed.
Preferably, the select circuit sequentially selects each of the plurality of memory circuits for a time necessary for the first test. Thus, first and second tests can readily be performed for all memory circuits.
Still preferably, the first test is the disturb test and the second test is the test other than the disturb test. In this case, the present invention is particularly effective.
In a method of testing a semiconductor according to the present invention, a test pattern generation circuit generating a control signal and an address signal for performing a first test is provided in a semiconductor memory device, then one memory circuit of a plurality of memory circuits is selected, the control signal and the address signal generated in the test pattern generation circuit is supplied to the selected memory circuit, and a control signal and an address signal for performing a second test is supplied from a source external to the semiconductor memory device to other memory circuits. Thus, as the first test can be performed for the selected memory circuit while the second test is performed for other memory circuits, test time can be reduced compared with the conventional procedure where first and second tests cannot simultaneously be performed.
Preferably, the first test is the disturb test and the second test is the test other than the disturb test. In this case, the present invention is particularly effective.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.